Design a scan able 4-bit binary counter with synchronous active high reset and ripple carry output using the scan able flip-flop illustrated in Figure 16.8a. Sketch the CLK, SCAN, and SD inputs required to shift the vector 1101 to the QD-QA outputs, latch the response of the combinational logic, and shift out the response (reset the counter to 0000 before performing the scan sequence). Sketch the output at SQ as the scan sequence is performed.