Q. What happens when a negative bias is applied to the gate of a FET?
The result of applying a negative bias to the gate is to reach the saturation level at a lower level of VDS where VDS is the voltage between the source and the drain. The resulting saturation value for ID has been reduced and it will continue to decrease as VGS becomes more and more negative. The pinch off voltage continues to drop in a parabolic manner as VGS becomes more and more negative. Eventually, VGS when VGS = -VP will be sufficiently negative to establish a saturation level and for all practical purposes the device has been "turned off".