Q. Explain from the drain characteristics that a JFET has infinite resistance?
When VGS = 0v
when a positive voltage Vds has been applied across the channel and the gate has been connected directly to the source to establish the condition VGS=0v.The result is a gate and source terminal at the same potential and a depletion region in the low end of each p- material .the instant the voltage VDD= VDS is applied ,the electrons will be drawn to the drain terminal ,establishing a conventional current ID, here ID=IS..It is important to note that the depletion region near the top of both the p-materials are wider this is due to the fact that the upper region is more reverse biased than the lower region that is the the greater the applied reverse bias ,the wider the depletion region .the fact that the p-n junction is reverse biased for the length of the channel results in a gate current of zero amperes .The fact that IG = 0A is an important characteristics of the JFET .
As the voltage VDS is increased from 0V to a few volts ,the current will increase as determined by ohms law and the plot of ID versus VDS will appear as shown in the graph.The relative straightness of the plot reveals that for the region of low values ot VDS, the resistance is essentially constant . As VDS increases and reaches upto a value vp,the depletyion region will widen ,causing a noticeable change in the channel width.The reduced path of conduction causes the resistance to increase and the curve in the graph to occur.The more horizontal the curve the higher the resistance ,suggesting that the resistance is approaching infinite ohms in the horizontal region.
If VDS is increased to a level where it appears that the two depletion regions would touch a condition reffered to as pinch -off will result .The level of VDS that establishes this condition is refferd to as pinch -off voltage and it is denoted by VP.In actuality the term pinch-off is a misnomer in that it suggests the current ID is pinched -off and drops of to 0A .In reality a very small channel exsists ,with a current of very high density .The fact that ID does not drop off at pinch-off and maintains saturation level .It is verified by the fact that the absence of a drain current would remove the possibility of different poyential levels through the n-channel material to establish the varying levels of reverse bias along the p-n junction .The result would be a loss of the depletion region distribution that caused pinch off in the first place.As VDS is increased by VP the region of close encounter between the two depletion regions will increase in length along the channel ,but the level of ID remains exactly the same ,therefore once VDS>VP the JFET has the characteristics of a current source.