Assume a 5 stage pipelined MIPS processor with stages IF, ID, EX, MEM and WB. LOAD and STORE are the only instructions accessing memory. Branches are resolved at ID stage.
(a) Give a code sequence that has data hazard which can be solved by forwarding.
(b) Give a code sequence that has data hazard that cannot be solved by forwarding. Indicate stall cycles required.
(c) Explain branch hazards. Why do branch hazards degrade the performance?