Overall Program Objective:
You will design and simulate a basic RISC processor. You will create and encode an instruction set. Your final task will be to "compile" a program into your processor's machine code, and execute that program on your simulated processor.
DESIGN AN INSTRUCTION SET
Part 1 Objective:
For this first stage of the project, you should design and encode your own original instruction set. You will design both an assembly language and a machine code. To complete this stage, you must do the following:
- List all of your registers
- List all of your instructions, and indicate what operands each instruction requires.
- Create a unique numerical encoding for each instruction, and list out the encoding
- Prove that your instruction set is Turing Complete.
- Translate the C program given in this project into your assembly language and machine code.
Limitations:
Your instruction set must conform to the following limitations:
- Your instruction set must be Turing Complete.
- You should not directly reproduce any existing instruction set (you may, of course, borrow instructions here and there).
- Your processor must be able to access at least 256 bytes of memory, where each memory entry is 1 byte long. You may access more, but are not required to.
- Your processor should start executing at address 0
- You should be creative!
Designing an Instruction Set:
The following is an example Turing Complete instruction set that meets the requirements of the project:
registers:
4 one-byte general purpose registers: $r0-$r3, each of which holds a two's complement number A one-byte program counter
instructions:
ADD RA, RB add registers RA+RB, store result in RA
SUB RA, RB subtract registers RA-RB, store result in RA
LOAD RA, [RB] load 1 byte from memory at address in RB into RA
STORE RA, [RB] store 1 byte from RA into memory at address in RB
LUI RC, IMM load 4 bit immediate into upper 4 bits of RC, lower bits are unchanged
LLI RC, IMM load 4 bit immediate into lower 4 bits of RC, upper bits are unchanged
JALR RA, RB branch to address in RB, store PC+1 into RA
BEQZ RA, RB branch to address in RB only if RA contains zero
encodings:
ADD: 0 0 0 0 RA1 RA0 RB1 RB0
SUB: 0 0 0 1 RA1 RA0 RB1 RB0
LOAD: 0 0 1 0 RA1 RA0 RB1 RB0
STORE: 0 0 1 1 RA1 RA0 RB1 RB0
JALR: 0 1 0 0 RA1 RA0 RB1 RB0
BEQZ: 0 1 0 1 RA1 RA0 RB1 RB0
LUI: 1 0 RC1 RC0 IMM3 IMM2 IMM1 IMM0
LLI 1 0 RC1 RC0 IMM3 IMM2 IMM1 IMM0
all other bit combinations are "NOP" - the instruction does nothing
You may not use the above instruction set. However, you are required to show how each of the above eight instructions can be modeled by one or more of your own instructions.
Testing Your Instruction Set:
You should translate the following C program into your assembly language and into your machine code:
char x, n, i;
n=5;
x=0;
for (i=0; i!=n; i++)
x=x+i;
You may use registers for n and i, if you choose, but you must use address 0xA0 for x.
Part 1 Submissions:
- A list of your instructions and a description of what they do
- A list of all your registers and flags, and a description of how they are used
- The bit encodings for each of your instructions
- For each of the instructions from the example instruction set, an example of how that instruction can be simulated by your instructions
- The C program translated into your assembly language
- The C program translated into your machine code (include addresses)