Problem:
Using the circuit topology displayed in Figure, arrange to bias the NMOS transistor at ID = 0.5 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt =1.0 V, λ = 0, and kn =1 mA/V2. Use a gate-bias resistor of 10MΩ .Specify RS and RD to two significant digits.
