Problem
Consider the following pipelined processor with four stages. This pipeline has a total evaluation time of six clock cycles. All successor stages must be used after each clock cycle.
(a) Specify the reservation table for this pipeline with six columns and four rows.
(b) List the set of forbidden latencies between task initiations.
(c) Draw the state diagram which shows all possible latency cycles.
(d) List all greedy cycles from the state diagram.
(e) What is the value of the minimal average latency?
(f) What is the maximal throughput of this pipeline?