Problem
A nonpipelined processor X has a clock rate of 250 MHz and an average CPI (cycles per instruction) of 4. Processor Y, an improved successor of X, is designed with a five-stage linear instruction pipeline. However, due to latch delay and clock skew effects, the clock rate of Y is only 200 MHz.
(a) If a program containing 1000 instructions is executed on both processors, what is the speedup of processor Y compared with that of processor X?
(b) Calculate the MIPS race of each processor during the execution of this particular program.