It is required to design a cmos logic circuit that realizes, Computer Engineering

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It is required to design a cmos logic circuit that realizes

It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Yis to be low when an even number (0 or 2) of the inputs A, B, and Care high

(a) Give the Boolean function Y.

(b) Sketch a PDN directly from the expression for Y. Note that it requires 12 transistors in addition to those in the inverters.

(d) Find the PUN as a dual of the PDN in (c), and hence the complete realization.

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