Assume that the following snippets are executed on a pipelined MIPS processor with forwarding and predict-taken branch predictor: (20) A. Label1: LW R2,0(R2) BEQ R2,R0,Label OR R2,R2,R3 SW R2,0(R5) B. LW R2,0(R1) Label1: BEQ R2,R0,Label2 LW R3,0(R2) BEQ R3,R0,Label1 ADD R1, R3, R1 Label 2: SW R1,0(R2) Draw the pipeline execution diagrams for these codes assuming that there are not branch delay slots and that the branch executes in EX stage. In snippet A, the branch is taken twice and then not taken. In snipped B, first branch is taken once and second branch is also taken once.