(a) A CMOS digital logic circuit contains the equivalent of 4 million CMOS inverters and is biased at VDD = 1.8 V. The equivalent load capacitance of each inverter is 0.12 pF and each inverter is switching at 150 MHz. Determine the total average power dissipated in the circuit.
(b) If the switching frequency is doubled, but the total power dissipation is to remain the same with the same load capacitance, determine the required bias voltage.