The Full Adder Instructions:
Questions for Part 1
1) How could you configure a full adder to operate as a half-adder?
2) Do the outputs of the full adders in Table 6-2 and Table 6-3 match the expected values in Table 6-1?
3) What advantage, if any, does the full adder in Digital_Exp_06_Part_01b have over the full adder in Digital_Exp_06_Part_01a?
Questions for Part 2
1) The AND gates in Digital_Exp_06_Part_02a serve to buffer the DIP switch settings for the hexadecimal displays. One input of each 2-input AND gate between the input DIP switches and rest of the circuit is tied to VCC (logic 1). Does this change the logic state of the DIP switch settings seen by the adders?
2) How would you modify the circuit in Digital_Exp_06_Part_02a to create a 12-bit adder? What additional parts would the circuit require?
3) How does the converter circuit of Digital_Exp_06_Part_02b convert the 4-bit binary value from the DIP switch to a BCD value?
4) Why do the digits on the displays in Digital_Exp_06_Part_02c sometimes briefly "flicker" when you change the DIP switch settings from one binary number to another?
Attachment:- The Full Adder.rar