How to reduce the overall voltage gain
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Q: A CS amplifier using an NMOS transistor with gm = 2 mA/V is found to have an overall voltage gain of -10 V/V. What value should a resistance Rs inserted in the source lead have to reduce the overall voltage gain to -5 V/V?
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A CS amplifier using an NMOS transistor with gm = 2 mA/V is found to have an overall voltage gain of -10 V/V
The overall voltage gain of a CS amplifier with a resistance Rs = 0.5 kO in the source lead was measured and found to be -10 V/V
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