Problem
1. Why must DRAMs be refreshed, and how may a refresh operation be carried out?
2. What is the maximum refresh period for typical 64-K-, 256-K-, and 4-Mbit DRAMs, respectively?
3. Why is there a limit of 10,000 ns on the time for which RAS* or CAS* can be active-low? What is the meaning of precharge time and what effect does it have on the design of DRAM systems?
The response should include a reference list. Double-space, using Times New Roman 12 pnt font, one-inch margins, and APA style of writing and citations.