how many and gates are required to realize y
How many AND gates are required to realize Y = CD+EF+G ?Ans. Y = CD + EF + G for realize this two AND gates are needed (for CD and EF).
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in successive-approximation ad converter offset voltage equal to 12 lsb is added to the da converters output this is done to ans it is done to reduce
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1s complement representation of decimal number of -17 by using 8 bit representation is ans 1710 100012in 8 bit 000100011s complement
the excess 3 code of decimal number 26 is ans 2610 in bcd is 00100110 bcdadd 011 to all bcd 01011001 for excess -
how many and gates are required to realize y cdefg ans y cd ef g for realize this two and gates are needed for cd and
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which ttl logic gate is used for wired anding ans open collector output ttl logic gate is
cmos circuits consume power ans as in cmos one device is on and one is always off therefore power consumption is low or can say less than
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