Given the subsequent FIFO and rules, how deep does the FIFO require to be to stop underflow or overflow?
RULES:
a. frequency(clk_A) = frequency(clk_B) / 4
b. period(en_B) = period(clk_A) * 100
c. duty cycle(en_B) = 25%
Suppose that clk_B = 100MHz (10ns)
By a. clk_A = 25MHz (40ns)
By b. period(en_B) = 40ns * 400 = 4000ns, but we merely output for 1000ns, because of c., so 3000ns of make possible we are doing no output work. Thus, FIFO size = 3000ns/40ns = 75 entries.