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For a particular inverter design using a power supply vdd

For a particular inverter design using a power supply VDD with VOL = 0.2VDD, VOH = 0.6VDD, VIL =0.4VDD, and VIH = 0.3VDD. In order to maintain noise margins of at least 0.15V for both noise marginhigh (logical 1) and noise margin low (logical 0), what are the requirements of VDD?

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