Op-Amp Design Project Tips and Suggestions
1) Before attempting any design in Cadence, start with a "back-of-the-envelope" design. To do this, you will need some basic transistor parameters (k'N, k'P, λN, λP...). These can be obtained by simulating a single transistor, examining its operating point and then calculating from the values of gm, Vdsat, gds, etc. The back-of-the envelope design should give you an idea of how many μf's you need for a given current consumption, where you should probably add a factor of 4 or so for margin (impedances in parallel, etc.).
2) As you start putting together you circuit and simulating its response, scale the complexity gradually. Do not try to put everything together at once. Ways to do this are:
a. Start with ideal current sources or voltage sources, allowing you to get the basic gain stage(s) working properly.
b. Start with a single-ended op-amp output and then go fully-differential once the single-ended is working properly. This postpones the CMFB design until a later step.
3) Leave yourself a "trail of breadcrumbs" to follow when things don't work as expected. Frequently make copies of your design. When something gives a good result, save a copy, giving it a recognizable name (i.e., schematic.1.good-gain, schematic.2.single-ended, etc.). Similarly, save multiple copies of your simulation state to capture the design variables which are providing good results.
4) Add comments (text) to your schematic. You should annotate the current per "leg", the performance achieved, what still needs to be done to the circuit. When leaving for the night, you can leave yourself a note to help you pick up where you left off. Good circuit schematics, like good code, are well annotated. More than anything else, this helps you when you come back to look at a circuit after a longer break.
5) If you find yourself going around in circles for the simulation, STOP, and try to think through what you are trying to achieve. Using a circuit simulator should follow the scientific method as much as possible: (a) understand the problem, what it is you are trying the achieve; (b) research approaches to solving the problem; (c) predict the result you expect to achieve; (d) run the simulation; and (e) come up with a conclusion and reconcile the simulated results with the original hypothesis. Note that all of these steps involve using your brain along with the simulator.
6) Pay close attention to your DC operating point. When adding new things to a schematic, it is easy to assume that the transistors are biasing properly and that the circuit is not working for some other reason. It may just be that the transistor you added is not biased in saturation which is killing your gain. Annotate the schematics with the DC operating points and check that transistors are biased properly.
7) During the design process, take advantage of the ideal components you have at your disposal. For example, if you care about the difference between two voltages, you can insert a voltage-controlled voltage source (vcvs) to measure that difference for you. If you care about the current, add a zero-valued DC voltage source to serve as an ammeter. Finally, the ideal_balun component greatly helps in the simulation of fully-differential circuits. This ideal transformer can be used to combine common-mode and differential-mode signals at the input and to obtain the differential-mode and common-mode signals at the output. To figure out which node is which on the ideal_balun, you can select each pin and query the properties (p=positive node, n=negative node, d=differential node, c=common node).
8) Divide and conquer. Break up your design assignments efficiently for your team. To do this well, you should agree upon specifications for the individual sub-circuits. For example, one person can be responsible for the design of the bias network and the gain-boosting amplifier, whereas the other student can be responsible for the design of the input Gm-cell and the output load. Both can work together on compensation, common-mode feedback, and report-writing. Other work partitions are possible. Again, for this to succeed, make sure you agree upon common specifications for each component.
To incorporate each other's designs, you will need to define each other's libraries in your cadence session. Also, each individual circuit should be created as a subcircuit, with pins, symbols, etc.
In two-person teams, you are to design a CMOS Low-Power Operational Transconductance Amplifier in 90-nm CMOS which meets the specifications listed below
|
Parameter
|
Required Specification
|
|
Low Frequency Gain
|
95 dB (56 V/mV)
|
|
Unity-gain Bandwidth
|
500 kHz (must be single-pole response)
|
|
Phase margin
|
75 deg, for unity gain feedback, no external load
|
|
Settling time
(1% of final value)
|
<6 msec (0.1% settling to final value) with 3pF external cap load
|
|
Output Swing
|
1.4 V-pk-to-pk differential (ppd)
|
|
Input common-mode range
|
At least 0.7-V overlap with the output signals
|
|
CMRR
|
>70 dB
|
|
PSRR+
|
>90 dB
|
|
Supply Voltage
|
1.5 V
|
|
Power dissipation
|
Pdiss < 30 mW
|
|
Slew rate
|
>0.2 V/usec
|
|
Input-Referred Noise Voltage Floor
|
<70 nV/√Hz in white portion
(should be white around 10-100 kHz).
Also, you must report the 1/f corner frequency
|
You must use the transistors in the 90nm GPDK, 1.2-V transistors. Additionally, you must design the op-amp to achieve one of the three following specifications listed below. Each additional spec met adds three points to your project grade-maximum of 9 points, where only one additional spec is minimum requirement needed to get 100.
1. Rail-to-rail operation, achieving common-mode input range of 0 to 1.5 V.
2. Fully differential output with embedded common-mode feedback, CMFB phase margin >75 deg.
3. Output buffered, including an output buffer capable of driving a load of 100 ohm in parallel with 3 pF. You can double the total op-amp power consumption. Also, if you choose this option, you must simulate the total harmonic distortion of the op-amp when placed in a negative feedback configuration with feedback resistors of 390ohm, load resistances of 800ohm, with closed-loop gain of 1. THD should be 0.1% or less.
Your design will be evaluated against the required specifications and then additional requirement #1-#3. You should refer to some typical op-amp data sheets to get a feel for typical performance results and how data is reported this is an op-amp I used for evaluating feasibility of the specs). The design is to be completed using Cadence for all circuit simulation. Tutorials are provided on-line on how to set up and use these tools. You will be using the 90-nm GPDK design kit from Cadence.
Your circuit design must meet the following requirements:
1. No external bias other than a single power supply and common mode input voltage is allowed. You must provide your own bias circuits for currents and voltages.
a. Ideal voltage and current sources are not allowed in your final circuit. Points will be deducted from your project grade if ideal sources are found in your netlist. Points will be deducted if voltage-mode biasing is found.
2. You must implement supply-independent biasing.
3. You must compensate all feedback networks. This applies to common-mode feedback as well as any internal amplifiers used (i.e., for active cascodes). All loops must have the 75-deg phase margin.
4. No resistors (or series resistor chains) larger than 50k are allowed, as they take too much area.
5. All NMOS transistor bodies must be connected to ground; PMOS transistor bodies should be connected to VDD.
6. Your design must use hierarchy (no flat netlists), with at least the following levels
- External testbench which only includes input AC and common-mode sources, power supply, ideal baluns, and the op-amp subcircuit.
- The primary OTA/op-amp
- Subcircuits for bias networks, additional amplifiers used for active cascade, common-mode feedback.
Attachment:- Assignment.rar