Write a test bench to simulate the state machine of Exercise 5.5 and verify the VHDL model by simulation.
Exercise 5.5
Draw an ASM chart to describe a state machine that detects a sequence of three logical 1s occurring at the input and that asserts a logical 1 at the output during the last state of the sequence. For example, the sequence 001011101111 would produce an output 000000100011. Write a two-process VHDL description of the state machine.