Response to the following :
It is required to design a MOS differential amplifier to have aCMRRof 80 dB. The only source of mismatch in the circuit is a 2% difference between the W/L ratios of the two transistors. Let I =100 μA and assume that all transistors are operated at VOV = 0.2 V. For the 0.18-μm CMOS fabrication process available, V1A = 5 V/μm. What is he value of L required for t e current-source transistor?