Develop a Verilog model for a peak detector that finds the maximum value in a sequence of 10-bit unsigned integers. A new number arrives at the input during a clock cycle when the data_en input is 1. If the new number is greater than the previously stored maximum value, the maximum value is updated with the new number; otherwise, it is unchanged. The stored maximum value is cleared to zero when the reset control input is 1. Both data_en and reset are synchronous control inputs.