The NMOS inverter with depletion load is shown in Figure(a). The bias is VDD = 2.5 V. The transistor parameters are VTND = 0.5 V and VTNL = -1 V. The width-to-length ratio of the load device is W/L = 1.
(a) Design the driver transistor such that vO = 0.05 V when the input is a logic 1.
(b) What is the power dissipated in the circuit when vI = 2.5 V?
