1. Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz. Assume the largest available capacitor is 50 pF.
2. With a finite op amp gain, the step response of an integrator is a slow exponential rather than an ideal ramp. Design an integrator whose step response approximates V (t) = αt with an error less than 0.1% for the range 0 0 (Fig. 8.65). Assume α = 10 V=µs, V0 = 1
