Design a binary divider which divides a 7-bit dividend by a 2-bit divisor to give a 5-bit quotient. The system has an input St that starts the division process.
(a) Draw a block diagram for the subtracter-comparator. You may use fulil adders or full subtracters.
(b) Draw a block diagram for the rest of the system (do not show the adders or subtracters in the subtracter-comparator block).
(c) Draw the state graph for the control circuit. Assume that the start signal (St) is present for one clock period.
(d) Give the contents of the dividend register and the value of Cat each time step if initially the dividend is 01010011 and the divisor is 11.