Describing switch-level modeling and vector in verilog

Question

1) Draw a 4-bit carry look ahead adder and write down the verilog HDL for it.

2) Draw 4X1 multiplexer and write down the HDL for it in all four modelling:

3) Briefly describe behavioral modelling (all functions) with suitable example:

4) Sketch and develop a project in HDL to compare x₅x₄x₃x₂x₁x₀ with y₅y₄y₃y₂y₁y₀. Test the output by means of test bench.

5) Describe the following with suitable example:

i) Tasks and functions

ii) Test bench for multiplexer

iii) Write down difference between always and initial.

iv) Blocking and non-blocking statements

6) Write down the two blocks in behavioural modelling.

7) What do you mean by FSM?

8) What do you understand by Data flow model?

9) What do you mean by Switch-level modeling?

10) Describe vector in verilog in detail.

11) Write down the different types of modeling Verilog?