Consider another possibility for the circuit in Fig. 16.7: Relabel the R input as S and the S input as R. Let S and R normally rest at VDD. Let the flip-flop be storing a 0; thus VQ = 0 V and VQ = VDD. To set the flip-flop, the S terminal is lowered to 0 V and the clock φ is raised to VDD. The relevant part of the circuit is then transistors Q5 and Q2. For the flip-flop to switch, the voltage at Q must be lowered to VDD/2. What is the minimum required W/L for Q5 in terms of (W/L)2 and ( μn/μp ) ? Assume Vtn = |Vtp |.
