Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.:
• a one clock cycle fetch
• a one clock cycle decode
• a four clock cycle execute
and a 50 instruction sequence:
?• no pipelining would require _____ clock cycles:
• a scalar pipeline would require _____ clock cycles:
• a superscalar pipeline with two parallel units would require ______ clock cycles: