Consider a 32-bit RC adder unit in which internal carry signals aregenerated using CMOS technology with as few transistors aspossible. Assume that each sum bit is connected to the S input ofthe corresponding gated SR latch. What is the minimum duration required to maintain the Clk input at Gnd such that the contents ofthe gated SR latches correctly reflect the outcome of the additionoperation? Assume that k'n=20μA/V2,k'p=0.4k'n ,Wn/Ln=WP/LP=10 ,VDD=5V, and that any load capacitance is equal to C=150fF