1) Describe Sequential and Concurrent assignments with an example in detail.
2) Illustrate the following terms:
a) Transport delay
b) Delta delay
c) Inertial delay.
3) Explain the Wait statement with appropriate example.
4) Explain the component declaration and Component instantiation in detail.
5) Describe about the Subprogram overloading and Operator over loading in detail.
6) Explain the guarded Signals with an appropriate example.
7) Describe the modelling synchronous logic with an appropriate example.
8) Describe the Modelling Moore FSM by giving the suitable example.
9) Explain the Verilog Structural modeling by giving the suitable example.
10) Describe the Operands and Operators in Verilog in detail.