Compare the performance (using AMAT) of a one-level split cache and a two-level unified cache system. For the one-level split cache, suppose a hit takes 2 clock cycles and the miss penalty is 100 clock cycles. Assume 20% memory accesses are data transfer. In 1000 memory references there are 20 misses for the instruction cache, and 50 misses for the data cache. In the two-level cache, assume that the miss rates for the L1 cache and the L2 caches are 5% and 2%, respectively. Assume the miss penalty from the L2 cache to memory is 100 cycles, the hit times of the L1 and L2 caches are 1 and 10 clock cycles, respectively.