Problem - Consider the CMOS Inverter shown in page 3 supplied with a bias of VDD = 5 V. The technology file for this CMOS is provided in Page 4. Only key design parameters are shown in CMOS mask layout. Grid size shown is 1 µm.
a) TABULATE the areas and perimeters of gate, source, and drain for both nMOS and pMOS transistors (with correct unit).
b) Calculate parasitic capacitances (Cgd, Cgs, Cdb, Cbs) for transistors at zero bias. For Cdb and Cds consider only the junction and sidewall effects. TABULATE your results for both pMOS and nMOS.
c) Calculate VTC inverter parameters: VOH, VOL, VIL, VIH. TABULATE results.
d) Use OrCAD/PSPICE to simulate and examine results in part (c). TABULATE results.
e) For part (d) show CMOS current level at VOH, VOL, VIL, and VIH. OrCAD only. TABULATE results.
f) Construct a load capacitance (CL) for CMOS circuit assuming that:
CL = 10XΣ2 transistors (Cgd + Cbd + Cbs + Cgs).
g) Use OrCAD/PSPICE to simulate and obtain CMOS's response time: rise-time and fall-time. TABULATE results.
h) For part (d), (e), (f), and (g) MUST SUBMIT OrCAD's
1) Schematics,
2) CMOS parameters used,
3) simulated probe results.
Attachment:- IC Design Assignment.rar