Question:
Cache associativity: memory and cache blocks mapping
Consider a memory of 64 blocks (labeled 0 through 63) and a cache of 16 blocks (labeled 0 through 15). In the questions below, list only correct results.
(i) Under 2-way set associativity, to which blocks of cache may element 31 of memory go?
(ii) In the sequence of memory block references from the CPU [0,2,10,45,10,2,44,35,26,44,45,10], beginning from an empty cache, will layout for a direct mapped and a 4-way set associative cache differ? What will be the mappings between cache block number and memory block number in each case?