A CMOS circuit includes a pair of N-dopedregions, separated by a P-doped channel, as well as a P-dopedregions, separated by an N-doped channel. Although this formsPNP and NPN transistors, the bias of the regions is designed so the junctions are reverse biased and the electric field effects on the channel are supposed to control the MOS-FET transistor soperations. There is a failure mode of a CMOS circuit where the biasconditions are violated. What is the failure mode, what causes it,what effects does it cause, and what is the simplest recovery mechanism.