An unpipelined processor takes 8 ns to work on one instruction. It then takes 0.2 ns to latch its results into latches. I was able to convert the circuits into 8 sequential pipeline stages. The stages have the following lengths: 0.8ns; 1.2ns; 0.7ns; 1.4ns; 0.8ns; 0.4ns; 1.4ns; 1.3ns.
Answer the following, assuming that there are no stalls in the pipeline. Show your work to receive full credit.
a. What are the cycle times in both processors (in nano-seconds)?
b. What are the clock speeds in both processors (in MHz)?
c. What are the IPCs in both processors?
d. How long does it take to finish one instruction in both processors (in nano-seconds)?
e. What is the speedup provided by the 8-stage pipeline?
f. If I was able to build a magical 1000-stage pipeline, where each stage took an equal amount of time, what speedup would I get?