a) A sequential circuit hast two inputs (w1 and w2) and one output (z). Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces a z=1; otherwise, z=0. For example: w1 : 0 1 1 0 1 1 1 0 0 0 1 1 0 w2 : 1 1 1 0 1 0 1 0 0 0 1 1 1 z : 0 0 0 0 1 0 0 0 0 1 1 1 0 Derive the state diagram, state table and a suitable circuit. Explain in detail your results.
b) Write VHDL code for the FSM described in part a)