A memory system is needed in a new design to support a small amount of data storage outside of the processor. The design is o be based on the 16 K bit CY7C128A SRAM organized as 2 K x 8.
(a) Provide a high-level block diagram for such an interface.
(b) Provide a high-level timing diagram for the interface to the SRAM from the microprocessor, assuming that seperate address and data busses are available. Define any control signals that may be necessary.
(c) Design the interface based on the timing diagram from part (a)
(d) Analyze the memory performance for a write and read operation of 1, 10, and 100 bytes.