A serial 2s complementer is to be designed. A binary integer of arbitrary length is presented to the serial 2s complementer, least signi?cant bit ?rst, on input X. When a given bit is presented on input X, the corresponding output bit is to appear during the same clock cycle on output Z. To indicate that a sequence is complete and that the circuit is to be initialized to receive another sequence, input Y becomes 1 for one clock cycle. Otherwise, Y is 0.
(a) Find the state diagram for the serial 2s complementer.
(b) Find the state table for the serial 2s complementer.