A serial leading-1s detector is tobe designed. A binary integer of arbitrary length is presented tothe serial leading-1s detector, most significant bit first, oninput X. When a given bit is presented on input X, thecorresponding output bit is to appear during the same clock cycleon output Z. As long as the bits applied to X are 0, Z=0. When thefirst 1 is applied to X, Z=1. For all bit values applied to X afterthe first 1 is applied, Z=0. To indicate tha sequence is completeand that the circuit is to be initialized to receive anothersequence, input Y becomes 1 for one clock cycle. Otherwise,Y=0.
a. Find the statediagram for the serial leading-1s detector.
b. Find the statetable for the serial leading-1s detector.