A 74x163 counter is hooked up with inputs ENP, ENT, and D always HIGH, inputs A, B, and C always LOW, input LD_L = (QA.QC)', and input CLR_L = (QB.QD)'. The CLK input is hooked up to a free-running clock signal. Draw a logic diagram for this circuit. Assuming that the counter starts in state 0000, write the output sequence on QD QC QB QA for the next 15 clock ticks.