design a CMOS logic circuitsthat realizes a three-input even-parity check. Specifically, theoutput Y is to be low when an even number (0 or 2) of the inputs A,B and C are high.
(a) Give the Boolean function Y .
(b) Sketch a PDN directly from the expression for Y. Note that it requires 12 transistors in addition to those in theinverters
(c) From inspection of the PDN circuit, reduce the number of transistors to 10
(d) Find the PUN as a dual of the PDN in (c), and hence the complete realization.