Level-Sensitive Scan Design and System-level busses

Question

Describe the Level-Sensitive Scan Design and System-level busses.

Answer 1

IBm has designed different serial integrated scan architectures, referred to as the level-Sensitive Scan Design. This design utilizes the polarity-hold, hazard-free and level sensitive latch.

This DFT approach forms the use of a module’s or systems functional bus to control and observe the signals during the functional level testing. A test and/or maintenance processor, such as the ATE, appears as other element attached to the system’s busses.