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Hold and Halt states of 8085 microprocessor

Explain hold and halt states of the 8085 microprocessor.

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If HOLD line of the 8085 found high, µP enters into the HOLD state and provides out a HLDA (Hold acknowledge) signal. After identifying the HOLD signal, the µP delays executing any further machine cycles and tri-states the A and AD buses and also the IO/M, RD and WR lines. At the time of the HOLD state, the peripheral devices may gain control of data and address buses for sending the data to or from the memory in the direct manner. This mode of operation is known as direct memory access (DMA). Whenever a HLT instruction is executed, µP enters into the HALT state. It will stop microprocessor. The registers and the status flags stay unaffected. The µP may get out of this state only one clock cycle after the valid interrupt is identified or the RESET happens.

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