Theory of TTL Inverter and its Transfer Characteristic

Circuit Structure:

The circuit diagram of Transistor Logic inverter is as shown in figure below. This circuit overcomes the limitations of single transistor inverter circuit. A few of the notable features of the circuit structure of TTL Logic family are as:

A) An input transistor, T1, that performs a current steering function, can be considered of as a back-to-back diode arrangement.

Figure: Equivalent of Input Current-Steering Transistor

The transistor can work in either forward or reverse mode to steer current to or from T2. As it has a forward current gain, it gives a higher discharge current to discharge the base of T2 whenever turning it off.

B) The output transistor pair, T3 and T4 as shown in figure below are termed to as a totem-pole output, can actively sink or source current to or from capacitive loads and permits the output voltage to be stated independently of the load joined to the gate. Resistor, R3, serves to limit the current. Beneath steady-state conditions, just one transistor is ON at a time.


Figure: Output Current Driving Transistors


Figure: Circuit Diagram and Transfer Characteristic of a TTL Inverter

C) The diode D, serves to raise the effective VBE of T4 that allows T4 to be turned OFF before T3 turns ON fully. It prevents large surge currents from flowing whenever both transistors conduct during transitions among logic states. The drawback is that the high logic voltage is decreased by an amount of the diode drop as shown in figure below.

Figure: Use of Diode in Totem-Pole Output

D) At last, T2 is a “phase splitter” driving transistor to drive output phase. It permits the logic condition to be phase-splitted in opposite directions and hence the output transistors can be driven in anti-phase. This permits T3 to be ON whenever T4 is OFF and vice-versa as shown in figure below.


Figure: The Phase Splitting Stage

Logical Operation:

The logical functioning of circuit can be established by recognizing the state of conduction of each and every transistor in turn from input to output for all possible combinations of the input states. Transistors can be taken as either OFF or ON. Note that the input transistor, T1, might conduct in either reverse or forward mode. Drawing up a table of conduction states accordingly with reference to first figure gives:

INPUT      T1          T2          T3          T4                D            OUTPUT

LO         ONFOR     OFF       OFF     ONCUT-IN   ONCUT-IN          HI

HI          ONREV     ON        ON         OFF             OFF               LO

LO in - HI out and HI in - LO out => This is a logic inverter action
Transfer Characteristic:

The transfer characteristic can be assumed by applying a slowly increasing input voltage and determining the series of events that takes place with regard to modifications in the states of conduction of each and every transistor and the critical points at which the onset of such changes take place. Let consider the circuit and transfer characteristic of figure above.

Point A:

With input LO and the base current supplied to T1, this transistor can conduct in forward mode. As the only source of collector current is the leakage of T2 then T1 is driven to saturation. This makes sure that T2 is OFF that, in turn, signifies that T3 is OFF. Whereas there is no load exists, there are leakage currents flowing in the output phase that permit the transistor T4 and the diode D to be barely conducting the point of cut-in.


Vo = 5 – 0.6 – 0.4 = 4V

Point A: Vi = 0V, Vo = 4V

Point B:

Since the input voltage is gradually raised, the above condition prevails till, with T1 ON in saturation, the voltage at the base of T2 rises to reach the point of conduction and then:

Vi = VBE 2CUT-IN – VCE1 SAT = 0.6 – 0.1 = 0.5V

Point B: Vi = 0.5V, Vo = 4V

Point C:

Since the input voltage is further raised, T2 becomes more conducting, turning completely ON. Base current to T2 is supplied by forward biased base-collector junction of T1 that is still in saturation (that is, both junctions of T1 are forward biased). Ultimately, T3 reaches the point of conduction. This occurs when:


Vi = 0.7 + 0.6 – 0.1 = 1.2V

Note that with transistor T3 at cut-in, VBE 3 = 0.6V that means that the current via R2 is 0.6V/1kΩ = 0.6mA. With operation in linear active region, the collector current in T2 is αFIE2 ≈ 0.97 x 0.6 = 0.58mA. The voltage drop across R1 is then VR1 = 0.58mA x 1.6 kΩ = 0.94V. Beneath this case, the voltage drop across T2 is:

VCE2 = VCC – VR1 – VR2

VCE2 = 5 – 0.94 – 0.6 = 3.46V

This verifies that T2 is still operating in forward active mode.

With T3 beginning to conduct, there is a conduction path for current via T4 and the diode, D, that then turns completely ON. In this condition:

Vo = VCC – VR1 – VBE4ON - VDON

Vo = 5 – 0.94 – 0.7 – 0.5 = 2.86V

Point C: Vi = 1.2V, Vo = 2.86V

Point D:

Since the input voltage is further raised, T2 conducts more heavily, ultimately saturating. T3 as well conducts more heavily and ultimately reaches the point of saturation. As T2 becomes more conducting, its collector current rises. This in turn raises the voltage drop across R1 that in turn means that the voltage across T2, that is, VCE2, reduces. This falls below the need for conduction in T4 and the diode, D, and hence both of these turn OFF before the saturation of T3.

Whenever T3 reaches the edge of saturation then:


Vi = 0.8 + 0.7 – 0.1 = 1.4V

Vo = VCE3SAT ≈ 0.2V

Point D: Vi = 1.4V, Vo = 0.2V

Noise Margins:

By using points C and D on the transfer characteristic in first figure to recognize the critical points, we encompass:

ViLMAX = 1.2V        VOLMAX = 0.2V    NML = 1.0V
ViHMIN = 1.4V        VOHMIN = 2.8V    NMH = 1.4V

The manufacturer’s specification assures:

ViLMAX = 0.8V        VOLMAX = 0.4V    NML = 0.4V
ViHMIN = 2.0V        VOHMIN = 2.4V    NMH = 0.4V

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