Concept of Threshold Voltage and Depletion Region

Introduction:

It is significant for the purpose of device modelling for the circuit analysis and design to encompass a distinct definition of threshold of change from weak to strong inversion. In this concern, the threshold voltage is stated for an n-channel MOSFET as the value of gate-source voltage that gives similar concentration of electrons in an inverted n-type channel as there are holes in the p-type substrate. At this point, the surface potential of semiconductor is equivalent in magnitude however opposite in polarity to Fermi potential in the body substrate, Φs = -ΦF. An expression for threshold voltage in terms of device parameters will permit an understanding of the factors that influence it and how it might be controlled.

The Depletion Region:   

Whenever a small gate voltage is applied to MOSFET, a depletion region is made as holes are repelled back into the p-type substrate or as electrons engage the vacant states in the valence band at the surface of substrate. This gives mount to the depletion region beneath the oxide as a layer of negatively ionized fixed atoms which is as shown in figure below. This layer is initially considered to be devoid of all free carriers. This can be shown that the depth of depletion region is as follows:

Xd = √[(2ε |Φs - ΦF|)/(qNA)]

Where:

εs is the permittivity of semiconductor material.
   
Φs is the electrostatic potential at the surface of semiconductor-oxide boundary.
   
ΦF is the Fermi potential in the body of semiconductor substrate.

NA is the doping concentration of semiconductor substrate

q is the magnitude of charge on electron.

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Figure: Conditions in MOSFET with depletion region formed

The net ionisation charge per unit surface area in this region beneath the oxide layer, supposing ionisation of all dopant atoms present in it, can be received as:

Q = - q NA Xd = - √[2qNA εs s - ΦF|]

The threshold voltage is reached at onset of strong inversion in the induced channel. This takes place whenever the electrostatic potential at the surface is equivalent and opposite to that in main p-type substrate, Φs = -ΦF as shown in figure below. At this point, the depletion layer reaches a maximum depth and further raise in gate-source voltage beyond the threshold voltage generates negligible raise in the depletion depth. The total negative ionisation charge per unit surface area in the depletion region at this point, symbolized QB0, is then as follows:

QBO = - √[2qNA εs |-2ΦF|]

Threshold Voltage:

There are main four principal that influence the threshold voltage and each is considered in turn.

i) Work Function:

The work function of a material is the amount of energy required to eliminate an electron from the Fermi level to free space. The work function of the material employed for the gate, qΦM, is distinct from that of the semiconductor employed for the substrate, qΦS and it is this which gives mount to the in-built electric field across the oxide layer that develops when the materials join to form the MOSFET. The gate can be fabricated in metal or a highly conducting polysilicon and the consequence of this field across the oxide should be accounted for in determining the gate-source voltage needed to reach strong inversion. The contribution made to this voltage made by the dissimilarity in the work functions can be found more suitably as the difference in Fermi potentials of the substrate and gate materials. This is termed to as the gate-to-channel potential, ΦGC, as follows:

Work function component:

ΦGC = ΦS - ΦM = ΦF substrate -ΦF gate volts, a –ive voltage
   
Where:

ΦF = (kT/q) ln (ni/NA) for p-type and ΦF = (kT/q) ln (ND/ni) for n-type material.

Note that ΦF sub is negative for p-type material and positive for the n-type material.

ii) Surface Potential:

We already know that, when forming a channel the energy bands should bend at the surface of semiconductor to make the surface potential Φs = -ΦF. This needs a voltage change of -2ΦF that is positive for n-channel transistor as ΦF is a negative quantity for p-type substrate. As a result the contribution of band bending in the direction of threshold voltage is:

Surface potential component: - 2 ΦF volts; a +ive voltage

iii) Depletion Charge:

Ionisation of the dopant atoms in depletion region should occur before a strong-inversion conducting channel can be made. This charge is given above per unit area of MOS capacitor structure as QB0. An equivalent and opposite charge should be accumulated on the gate of transistor and the voltage related with forming this charge is simply obtained from the law of capacitor Q = CV or V = Q/C as follows:

Depletion charge component:

- (QBO/COX) = √(2qNAεs |- 2 ΦF |)/COX Volts; a +ive voltage

iv) Impurity Charge:

The boundary between the oxide and semiconductor in practice is not ideal due to impurities in the materials and lattice imperfections. This gives mount to a small quantity of positive impurity charge at the lower edge of oxide, QOX, per unit area. This requires to be compensated for by a negative charge at the gate electrode and thus makes a contribution to threshold voltage of:

Impurity charge component:

- (QOX/COX) volts a –ive voltage

If all of such contributions are joined then the threshold voltage is as follows:

VTO = ΦGC – 2 ΦF – (QBO/COX) – (QOX/COX) volts

This is a positive voltage for the n-channel MOSFETs.

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Figure: Conditions in MOSFET at Threshold, VGS = VT, VDS=0

Body Effect:

All consideration of the operation of n-type MOS transistor therefore far has supposed that the source and body substrate encompass both been joined to ground. Beneath this condition the threshold voltage is designated VT0 as above. In several circuits, though, the source might sit at a higher potential than the substrate and hence there is a voltage difference between them, VSB. This signifies that in forming the depletion region there is an additional bias and hence the surface potential of Φs = -ΦF exists on one side of this region whereas a potential of VSB exists on the other side. This signifies that the ionisation charge is modified and hence:

QB = - √2qNAεs |- 2 ΦF + VSB|

The threshold voltage will as well be modified to provide:

VT = ΦGC – 2 ΦF – (QB/COX) – (QOX/COX)

On rearranging this:

VT = ΦGC – 2 ΦF – (QB/COX) – (QOX/COX) – [(QB - QBO)/COX]

That can be written as:

VT = VTO - [(QB - QBO)/COX]

On substituting:

VT = VTO + √[(2q NA εs |- 2ΦF + VSB|) - √(2q NA εs |-2ΦF|)]/COX

VT = VTO + [√(2q NA εs) (√|-2ΦF + VSB| - √|-2ΦF|)]/COX

This gives the most general form for the threshold voltage as:

VT = VTO + γ (√|-2ΦF + VSB| - √|-2ΦF|)

Where γ = (√2qNAεs)/COX is termed as the body-effect coefficient or the body factor.

Technology Considerations
:

The threshold voltage is possibly the most variable of all the properties of MOS transistor. Usual values range from around 0.5 to 1.5V and are generally close to 20% of the supply voltage in digital circuits. This is subject to both manufacturing and temperature variations. In practice, though, it can be controlled in the fabrication procedure. A general practice nowadays is to employ Polysilicon as the material for forming the gate instead than aluminium metal. This lowers the work function difference among the gate and the substrate and as a result lowers the threshold voltage. This is useful in low-voltage (3V and 3.3V) logic technologies.

The other process utilized is that of ion implantation into the substrate just underneath the oxide that can be employed to increase or lower the threshold voltage. For an n-channel device, the implantation of positive ions lowers the threshold voltage as the implantation of negative ions raises it. With adequate ion implantation it is probable to lower and even reverse the threshold voltage. This signifies that depletion mode devices can be fabricated that have a conducting channel formed with zero gate-source voltage applied, in contrast to improvement type devices already explained. This is helpful in analogue and mixed signal circuit design although it does make the fabrication cycle longer and more costly, and is thus avoided in purely digital technologies.

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