MOS Transistor Inverter: Static Characteristics II

MOS Inverter Voltage Transfer Characteristic:

The schematic figure of simple MOS transistor inverter with a resistive load is repeated in figure shown below. Since with the simple bipolar transistor inverter, the transfer characteristic can be plotted as output voltage against input voltage, V_o vs. V_in as shown in figure below.

Figure: Schematic Diagram of Simple MOS Inverter

Initially, with V_i = 0 the input voltage to transistor is beneath threshold voltage and the transistor is OFF or non-conducting and therefore the output voltage is pulled up to the supply voltage V_DD. Once the input voltage is raised to be equivalent to the threshold voltage, V_T, the transistor starts to conduct and therefore the output voltage drops. As V_DS > V_GS – V_T, the transistor operates initially in saturation region. Since the input voltage is further raised, the output voltage continues to drop until ultimately V_DS < V_GS – V_T and the transistor comes out of the saturation region to operate in non-saturation region. Ultimately the input voltage reaches an utmost of V_DD and the output reaches its minimum value of V_OL as formerly computed.

Figure: Voltage Transfer Characteristic of Simple MOS Transistor Inverter

Critical Logic Voltages:

The similar critical input and output logic voltages can be stated as for other logic families viz.:

V_iLMAX = maximum voltage acceptable as the logic LO input

V_iHMIN = minimum voltage acceptable as the logic HI input.

V_OLMAX = maximum voltage acceptable as the logic LO output.

V_OHMIN = minimum voltage acceptable as the logic HI output.

a) Critical Point V_{iL MAX}, V_{OH MIN}:

This is the point on upper left-hand portion of transfer characteristic where the slope is -1. At this point, the transistor can be taken to operate in the saturation region where, neglecting the consequences of channel length modulation for simplicity, the drain current is explained as:

I_D = K_n(V_GS - V_T)²

However as V_O = V_DS and V_i = V_GS and V_O = V_DD – i_DR_D then:

V_o = V_DD – K_nR_D (V_i - V_T)².......................... (a)

On expanding it gives:

V_o = V_DD - K_nR_DV_i² + 2 K_nR_DV_iV_T - K_nR_DV_T²

On differentiating:

∂V_o/∂V_i = - 2 K_nR_DV_i + 2 K_nR_DV_T

At critical point ∂V_o/∂V_i = -1 with V_i = V_{iL MAX} and V_O = V_{OH MIN} and hence:

- 2 K_nR_DV_i + 2 K_nR_DV_T = - 1

2 K_nR_DV_iLMAX = 1 + 2 K_nR_DV_T

And hence,

V_iLMAX = V_T + 1/(2 K_nR_D)

This value is a slight higher than V_T and for illustration given with V_T = 1V, R_D = 100kΩ and K_n = 100µAV^-2, V_{iL MAX} = 1.05V.

Replacing back into equation (a) to find out the output voltage for this coordinate gives:

V_OHMIN = V_DD – K_nR_D(V_{iL MAX} - V_T)²

V_OHMIN = V_DD – K_nR_D[V_T + (1/ K_nR_D) - V_T]²

And hence ultimately:

V_OHMIN = V_DD – (1/4 K_nR_D)

This value is a slight lower than VDD and for illustration given with V_DD = 10V, V_T = 1V, R_D = 100kΩ and K_n = 100µAV^-2, V_{OH MIN} = 9.98V. The coordinate of critical point (a) is then:

V_iLMAX, V_OHMIN = 1.05, 9.98 V

b) Critical Point V_{iH MIN}, V_{OL MAX}

This is the point on lower right-hand portion of the characteristic where slope is -1. At this point, the transistor can be taken to operate in non-saturation region where the drain current is explained as:

I_D = K_n[2(V_GS - V_T)V_DS – V²_DS]

However again, as V_O = V_DS and V_i = V_GS and V_O = V_DD – i_DR_D then:

V_O = V_DD – 2 K_nR_D (V_i - V_T) V_o + K_nR_DV_o²

On expanding:

V_O = V_DD – 2 K_nR_DV_iV_o + 2 K_nR_DV_TV_o + K_nR_DV_o²

On rearranging:

V_O [1 - K_nR_DV_T] = V_DD - 2 K_nR_DV_iV_o + K_nR_DV_o²

There is a choice here to employ implicit differentiation to find ∂V_o/∂V_i or to re-arrange the expression as V_i in terms of V_O and then determine ∂V_i/∂V_o. The latter is simpler as there is just one term in V_i. Then,

2 K_nR_DV_iV_o = V_DD – [1 - 2 K_nR_DV_T]V_o + K_nR_DV_o²

And hence,

V_i = V_DD/(2 K_nR_DV_o) – [(1 - 2 K_nR_DV_T)/ 2 K_nR_D) + (V_o/2)............... (b)

Then,

∂V_o/∂V_i = - V_DD/(2 K_nR_DV_o²) + (1/2)

For ∂V_o/∂V_i  = -1 we can employ ∂V_i/∂V_o= -1 and hence:

- (V_DD/2 K_nR_DV_o²) + (1/2) = - 1

(V_DD/2 K_nR_DV_o²) = 3/2

V_o² = V_DD/3 K_nR_D

By taking the positive root as practical value gives:

V_OLMAX = √V_DD/3K_nR_D

That for the illustration given with V_DD = 10V, V_T = 1V, RD = 100kΩ and K_n = 100µAV^-2 , V_{OL MAX} = 0.58V.

This is significantly higher than the great value of VOL computed formerly. Then replacing this back into the expression for V_i in equation (b) above gives:

And therefore ultimately the critical input value is as shown:

V_iHMIN = V_T + 2√V_DD/3K_nR_D – (1/2 K_nR_D)

That for illustration given with V_DD = 10V, V_T = 1V, R_D = 100kΩ and K_n = 100µAV^-2 provides V_{iH MIN} = 2.1V. This gives the coordinates of critical point (b) as:

V_iHMIN, V_OLMAX = 2.1, 0.58 V

Noise Margins:

Ultimately, the noise margins for simple MOS inverter can be computed approximately from the critical points evaluated from the transfer characteristic as shown:

NM_H = V_OHMIN – V_iHMIN = 9.98 – 2.1 = 7.88V

NM_L = V_iLMAX – V_OLMAX = 1.05 – 0.58 = 0.47V

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