MOS Transistor Inverter: Static Characteristics I

Resistively Loaded Common-Source Amplifier:

The schematic figure of a common-source amplifier with a resistive load is as shown in figure below. The FET is biased into conduction with a d.c. bias voltage, V_GS, and an input signal, V_gs, is superimposed on this bias. The output voltage is examined across the drain-source of transistor.

Figure: Schematic figure of a Resistively Loaded MOSFET Amplifier

The amplifier has then both an input and an output circuit characterization as follows:

Input Circuit: V_i = V_GS = V_GS + V_gs           

Output Circuit: V_o = V_DS = V_DD – i_D R_D

By rearranging the second expression we get:     

V_DS/R_D = V_DD/R_D - i_D

And hence,

i_D = - (1/R_D) V_DS + (V_DD/R_D)                      

It is a straight-line relationship of the form y = mx + C, where m = -1/R_D and C = V_DD/R_D. This straight line states the locus of operating point for the output circuit of amplifier. This is termed to as the “load-line” of amplifier and can be plotted from two points:

If i_D = 0; 0 = - (1/R_D)    V_DS + (V_DD/R_D) => V_DS = V_DD, i_D = 0 Point 1   

If V_DS = 0; i_D = (V_DD/R_D) = I_{D MAX} => V_DS = 0, i_D = V_DD/R_D Point 2

This relationship can be superimposed on the set of characteristic curves of i_D vs. V_DS for transistor, as shown in figure below.

Operation as an Amplifier:

Figure below exhibits the locus of operating point of transistor on the load line whenever a signal is applied to the gate of transistor. Whenever the gate voltage is raised above the bias point the drain current rises in response. This in turn raises the voltage drop across R_D and as a result the output voltage drops. Whenever the input gate voltage is lowered from the bias value then the drain current reduces in response, the voltage drop across R_D drops and therefore the output voltage rises. This can be seen that the phase of output voltage is opposite to that of input and therefore this is an inverting amplifier. From the values given for signal levels, this can be seen that this phase consist only a small gain of less than 2.

Figure: Operation of MOS Transistor as a Voltage Amplifier

V_DD = 10V
                           
d.c. Bias Conditions: Input: V_GS = 4V; Output: V_DS = 5.8V, I_D = 37µA

a.c. Signal Conditions: Input: V_gs = 2V_ptp Output: V_ds = 3.5 V_ptp, i_d = 32µA _ptp

Voltage Gain: V_ds/V_gs = 3.5V/2V = 1.75 low gain

Operation as a Switch:

Figure below exhibits the operation of resistively loaded MOS transistor as the logic switch. The input voltage applied to gate is either logic LO at 0V or logic HI at V_DD. Whenever the input voltage is LO at 0V, then V_GS applied to the gate is beneath the threshold voltage of transistor, V_T, and the transistor is non-conducting or OFF. In this situation, the drain current is zero and there is no voltage drop across the load resistor, R_D, and hence the output voltage is pulled up to the supply rail, V_DD, as shown at point A on the characteristic. On other hand, when the input voltage applied is a logic HI value of V_DD, then the transistor becomes extremely conducting or ON and the drain current increases to its maximum value, I_{D MAX}. In this condition the output voltage goes to its logic LO level, V_OL, as shown at point B on characteristic. This can be seen to some finite voltage above zero that depends on the properties of transistor. With appropriate design, the value of V_OL can be maintained less than the threshold voltage, V_T, and hence this logic LO level can be accurately interpreted by the following logic gate.

Figure: Operation of MOS Transistor as a Logic Switch

Logic Voltages:

Input Voltages: For present, the input logic voltages will be taken as ideal and hence:

V_iL = 0V and V_iH = V_DD

Output Voltages: Whenever the input is at LO logic level, the transistor is OFF and the output will be pulled up to supply voltage and hence:

V_OH = V_DD

Whenever the input is at HI logic level, the transistor is operating in non-saturation region with utmost drain current flowing. The equation explaining the current-voltage relationship can be resolved beneath these conditions in order to find out the output logic LO voltage. Whenever operating in the non-saturation region the drain current is explained as:

I_D = K_n[2(V_GS - V_T) V_DS – V²_DS]

With conditions I_D = I_{D MAX}, V_i = V_GS = V_DD and V_DS = V_OL

On substituting it gives:

I_{D MAX} = K_n[2(V_DD - V_T) V_OL – V²_OL]

However from the circuit:

I_{D MAX} = (V_DD - V_OL)/R_D

Thus:

(V_DD - V_OL)/R_D = K_n[2(V_DD - V_T) V_OL – V²_OL]

Then,

(V_DD - V_OL)/(K_nR_D) = 2(V_DD - V_T) V_OL – V²_OL

On re-arranging it gives:

V_DD/(K_nR_D) = [(1/ K_nR_D) + 2(V_DD - V_T) V_OL – V²_OL

V²_OL – [(1/ K_nR_D) + 2(V_DD - V_T)]V_OL + V_DD/(K_nR_D) = 0

When it is supposed that 2(V_DD – V_T) >> 1/K_nR_D then this simplifies as:

V_OL = (V_DD - V_T) ± √(V_DD – V_T)² – (V_DD/K_nR_D)

One solution will encompass a value greater than the supply voltage, V_DD, and can be rejected to give the value that lies between 0V and V_DD and hence in the illustration given with V_DD = 10V, V_T = 1V, R_D = 100kΩ and K_n = 100µAV^-2:

V_OL = (10 -1) - √(10 -1)² – [10/(10^-4 10⁵)] = 9 - √81 -1 = 0.05V

This value is acceptable as it is much less than threshold voltage, V_T, and therefore can be applied as LO logic level to an identical circuit.

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