Theory of Current-Voltage Relationships

Current-Voltage Relationships:

Influence of Drain-Source Voltage:

The operation of MOS transistor up to now has supposed that the drain-source voltage, VDS, was equivalent to zero. This meant that conditions in the capacitive layer were controlled only by the gate-source voltage, VGS. It is as well possible to differ the drain-source voltage, VDS, and hence whenever a conducting channel has been formed, current can flow via this channel. The conditions in the channel and the current that flows via it are also dependent on the value of drain-source voltage applied.

i) Zero Drain-Source Voltage with Channel Formed, VGS ≥ VT, VDS = 0

Whenever the gate-source voltage is bigger than the threshold voltage, a conducting channel is build. The voltage VGS - VT can be considered of as the channel-forming voltage. When the drain-source voltage is zero this channel will be uniform all along its length as can be seen in figure below. The depletion region beneath the channel will too be uniform along the channel flanked by drain and source.

ii) Non-Saturation Region, VGS ≥ VT, 0 < VDS  ≤ VGS - VT   

Whenever the drain-source voltage is raised above zero an electric field now exists all along the length of channel, acting from drain to source that causes electrons in the channel to flow from source to drain. This gives mount to a conventional current flowing in the opposite direction from drain to source, termed to as the drain current, iD, of the transistor. This electric field as well causes the conducting channel to taper becoming narrower at drain end as shown in figure below. The depletion region as well becomes wider around the drain. This tapering of channel becomes more extensive as VDS is raised however is maintained less than the value VGS - VT. This region of operation of transistor is termed as the non-saturation region (frequently termed to a little confusingly as linear region). The drain current which flows also rises with increasing VDS, for a given value of VGS, however not in a linear fashion as shall be seen.

iii) Saturation Region, VGS ≥ VT, VDS  ≥ VGS - VT

When the drain-source voltage is further raised, it will be accompanied by a raise in drain current. Eventually, though, it will become equivalent to the channel forming voltage applied to gate, VDS = VGS - VT. Whenever this takes place, the tapering of channel becomes complete to the point that the channel becomes closed off at drain end as shown in figure below. This condition is termed to as ‘pinch-off’ of channel. It must be noted that efficiently what has happened here is that the voltage at the drain, associative to the source, has become equivalent to the channel forming voltage VGS - VT and hence the channel can’t remain established at drain. Once this occurs, the drain current becomes limited to its value at pinch-off and further raise in the drain-source voltage brings only a slight raise in drain current, that is, the drain current saturates. As a result, this region of operation where VDS > VGS - VT is termed as the saturation region. Most of the analogue circuits operate wholly in this region.

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Figure: Uniform Channel Formed in MOSFET with VGS > VT, VDS = 0

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Figure: MOSFET in Non-Saturation Mode, VGS >VT, 0 <VDS < VGS -VT

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Figure: MOSFET at Channel Pinch-Off, VGS > VT, VDS = VGS - VT

iv) Channel Length Modulation:

In older devices, where the length of channel is greater than the minimum technology dimension (that is, long-channel devices), the conditions in the channel remain at such of pinch-off once the saturation region is entered. Therefore the value of current for a given gate-source voltage remains steady at pinch-off value if operating in the saturation region. In more modern devices, where channel lengths are much shorter (that is, short-channel devices), the pinch-off condition extends all along the channel towards the source if VDS > VGS - VT, as shown in figure below. This efficiently shortens the channel slightly as VDS rises, a phenomenon termed to as channel length modulation. This, in effect, signifies that the depletion region starts to extend back towards the source. Though, current flow is maintained by the acceleration of electrons via this region in a thin film close to the surface of semiconductor beneath the influence of very high electric field here. Certainly, in saturation, the raise in VDS above the channel forming voltage is developed almost completely across the depletion region at the shortened end of channel. This shortening of channel as well permits the drain current to rise slightly if operating in the saturation region.

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Figure: Channel Length Modulation in MOSFET, VGS >VT, VDS >VGS-VT

Current-Voltage Relationships:

i) Non Saturation Region, VGS ≥ VT, 0 < VDS  ≤ VGS - VT

Figure below shows a diagram symbolizing the channel induced in MOS Transistor beneath the oxide whenever operating in non-saturation region. This can be seen to be wedge-shaped due to the influence of drain-source voltage. The x-direction will be taken as vertical direction beneath the oxide whereas the y-direction will be taken as horizontal distance all along the channel as shown below. It is supposed, for simplicity of analysis, that the threshold voltage is constant all along the length of channel and that the distribution of charge is consistent in any elemental section dy, containing a depth xc. When the drain-source voltage is zero, VDS = 0, the effective voltage making the channel is the gate-source voltage over and above the threshold voltage, VGS - VT. Whenever the drain-source voltage is not zero, the effective voltage making the channel is decreased by an opposing contribution from the drain-source voltage Vy and is altered to VGS - VT – Vy. This channel voltage differs as a function of y depending on position in the channel with Vy = 0 at y = 0, the source end and Vy = VDS at y = L, the drain end.

The net charge induced in channel per unit area of oxide at the point y, the position of elemental section dy, is then as follows:

Qy = COX (VGS – VT – VY)

The charge per unit volume in this part is then as follows:

ρy = QY/XC

It will be remembered that the drift current for electrons caused by an electric field E is as follows:

Idrift = JA = ρμnEA

Where the direction of current flow is same as the direction of electric field, applied to the elemental section of channel, dy, this provides the drain current:

ID = - ρy μn EyWxC

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Figure: Elemental Section of Channel with 0 < VDS < VGS - VT

As electric field is acting in the negative y direction. Replacing for ρy and taking the electric field as constant all along the elemental length, Ey = - dVy/dy provides:

ID = (Qy/XC) μn (dVy/dy) WxC = Qy μn W (dVy/dy)

This expression applying to elemental length dy can now be integrated all along the length of channel from source, y = 0 to drain, y = L and hence:

oL IDdy = oVDS Qy μn WdVy

Substituting for Qy from above:

oL IDdy = μn WCOX oVDS (VGS - VT - VY) dVy

And hence:

oL IDdy = μn WCOX [oVDS (VGS - VT) dVy - oVDS VY dVy]

Integrating then provides:

IDL = μn WCOX [(VGS - VT)VDS - (VDS2/2)]

And finally:

ID = (1/2)μn WCOX (W/L)[2(VGS - VT)VDS - VDS2]

The prefix constant term is termed to as the trans-conductance parameter, for MOSFET:

Kn = (1/2) μn COX (W/L) and consists of dimensions of AV-2 and hence:

ID = Kn [2(VGS – VT) VDS – V2DS]
      
This can be seen from this that the level of current flow in MOS transistor can be controlled by the physical dimensions of length L and width W in its fabrication. However it is such dimensions that are the principal tool at the disposal of circuit design engineer.

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Figure: Drain Current vs. Drain-Source Voltage in Long-Channel MOSFET

Figure below shows a plot of drain current vs. drain-source voltage with gate source voltage as an individual parameter. This can be seen that such curves contain a hyperbolic shape. Though, it is significant to remember that this relationship is valid just for operation in the non-saturation region where VDS ≤ VGS - VT.

Of interest is the point where maximum takes place on the curves. This can be found by differentiating the above expression for the drain current with respect to VDS and by equating to zero, we get:

∂ID/∂VDS = Kn [2(VGS - VT) – 2VDS] = 0

That is satisfied for VDS = VGS - VT.

This exhibits that the drain current reaches an utmost value at boundary between the non-saturation and the saturation region as shown in figure above.

i) Saturation Region:

For long-channel devices, this has been seen that the drain current saturates at its pinch-off value at VDS = VGS - VT and remains at this value in saturation region. Therefore, an expression for the drain current in saturation can be received by just substituting the boundary condition into the expression obtained for operation in non-saturation region. This provides:

ID = Kn [2(VGS - VT) (VGS - VT) – (VGS - VT)2]

That gives,

ID = Kn (VGS - VT)2

This relationship is as shown in figure above.

ii) Channel Length Modulation:

For short-channel devices, the consequence of channel length modulation should be accounted for. This can be seen in figure below that the drain current in such devices raises slightly in the saturation region as drain-source voltage is raised. Though, it can as well be seen that the slope in this region is steady pointing a linear dependency. This can be accounted for relatively just by comprising the channel length modulation factor, λ, that is applied to the drain current in saturation region. The expression for drain current is then modified to become:

ID = KN (VGS - VT)2 [1 + λVDS]

Where λ has dimensions of V-1 and has a usual value of 0.005 to 0.05.

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Figure: Drain Current vs. Drain-Source Voltage for Short-Channel MOSFET

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