Design of a 4 bit parity generator:
a) Using XOR gates design and simulate a 4 bit even parity generator. Draw the circuit in a way to minimize the propagation delay.
b) Hence build the adder circuit on breadboard and show the working circuit to the lecturer.
c) Describe the operation of a 74HC280 as a parity generator. Draw the schematic of a 74HC280 as a 4 bit even parity generator.
d) Using the appropriate datasheets find the propagation delay of the circuit built in a and b. Hence find the maximum frequency data can be presented to the circuit. Comment on the results.
e) Present the 1st page of the datasheet of each component used in solving task 2 as evidence that the appropriate datasheets have been referenced.