You are a thermal design engineer and plan to design cooling solution for computer chip. As a basic design, a chip (kc = 50 W/m-K) is mounted in a dielectric substrate (ks = 5.0 W/m-K) and one surface of the system is convectively cooled, while the remaining surfaces are well insulated from the surroundings. The chip in 3x9 mm atn the top middle of substrate which is 12x 27 mm. It is reasonably assumed that the system to be very long in the direction perpendicular to the paper, so that the problem is rendered into two-dimensional. Under steady operation, electric power dissipation in the chip provides for uniform volumetric heating at rate of q_dot = 1.5x107 W/m3. You are limited to forced air convection cooling with h = 250 W/m2·K and T00 = 40 oC. However, for the circuitry within the chip to survive, the chip temperature should not rise above 85 oC.
(a) Solve for the temperature distribution within the chip and dielectric mount (Figure 1) using a finite- difference method. A grid spacing of 3 mm is suggested. (Note that a symmetry condition exists.) Provide all discrete nodal equations (one for each different kind node), and show their derivations.
(b) Create T-x plot for each rows of nodal network (in one plot). Check if the package meets the industrial requirement (the maximum chip temperature of 85 oC), you will find that temperatures within chip easily rise higher than the requirement.