Write VHDL code for a shift register module that includes a 16-bit shift register, a controller, and a 4-bit down counter. The shifter can shift a variable number of bits depending on a count provided to the shifter module. Inputs to the module are a number N (indicating shift count) in the range 1 to 15, a 16-bit vector par_in, a clock, and a start signal, St. When St = ‘1', N is loaded into the down counter, and par_in is loaded into the shift register. Then the shift register does a cycle left shift N times, and the controller returns to the start state. Assume that St is only ‘1' for one clock time. All operations are synchronous on the falling edge of the clock.
(a) Draw a block diagram of the system and define any necessary control signals.
(b) Draw a state graph for the controller (two states).
(c) Write VHDL code for the shift-register module. Use two processes (one for the combinational part of the circuit, and one for updating the registers).